A New Error Correction Circuit for Delay Locked Loops

@article{Maillard2013ANE,
  title={A New Error Correction Circuit for Delay Locked Loops},
  author={Pierre Maillard and W. Timothy Holman and T. Daniel Loveless and Lloyd W. Massengill},
  journal={IEEE Transactions on Nuclear Science},
  year={2013},
  volume={60},
  pages={4387-4393}
}
  • Pierre Maillard, W. Timothy Holman, +1 author Lloyd W. Massengill
  • Published 2013
  • Physics
  • IEEE Transactions on Nuclear Science
  • A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100 MeV-cm2/mg show that the ECC mitigates missing pulses in DLLs fabricated at features… CONTINUE READING

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