A New Error Correction Circuit for Delay Locked Loops

@article{Maillard2013ANE,
  title={A New Error Correction Circuit for Delay Locked Loops},
  author={Pierre Maillard and W. Timothy Holman and T. D. Loveless and Lloyd W. Massengill},
  journal={IEEE Transactions on Nuclear Science},
  year={2013},
  volume={60},
  pages={4387-4393}
}
A new error correction circuit (ECC) for delay-locked loops (DLLs) using combinational logic and a “peeled” voltage-controlled delay line (VCDL) layout is proposed. The ECC can be used to mitigate missing output pulses due to single-event effects in scaled CMOS processes. The implementation of the ECC results in no significant area penalty or performance degradation of the DLL. Simulations at LETs up to 100 MeV-cm2/mg show that the ECC mitigates missing pulses in DLLs fabricated at features… CONTINUE READING

References

Publications referenced by this paper.
Showing 1-10 of 14 references

Radiation effects, predicted, observed and compared for spacecraft systems

  • B. E. Pritchard, G. M. Swift, A. H. Johnston
  • Proc. IEEE NSREC Radiation Effects Data Workshop…
  • 2002
Highly Influential
5 Excerpts

RHBD delay locked loops: Single event transient analysis, simulation, and hardening

  • P. Maillard
  • M.S.E.E. thesis, Dept. Elect. Eng., Vanderbilt…
  • 2010
3 Excerpts

Similar Papers

Loading similar papers…