A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%

@article{Laskar2018ANC,
  title={A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%},
  author={Nivedita Laskar and Suman Debnath and Alak Majumder and Bidyut K. Bhattacharyya},
  journal={Journal of Circuits, Systems, and Computers},
  year={2018},
  volume={27},
  pages={1-20}
}
The present methodology of clock distribution inside high-performance central processing unit chip o®ers current to ramp linearly or exponentially when the chip comes out of sleep mode to active mode or when the clock starts driving a chip to operate. This linear current ramp leads to power and ground noise due to Ldi/dt. In this paper, we have shown that for a given power delivery network (PDN), it is possible to generate a current pro ̄le (current versus time), by controlling the current on… CONTINUE READING

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Publications referenced by this paper.
SHOWING 1-10 OF 29 REFERENCES

LECTOR based clock gating for low power multi-stage °ip-°op applications, 16th Int. Conf. Electronics, Information, and Communication (ICEIC 2017), IEIE, Phuket, Thailand

  • P. Bhattacharjee, B. Nath, A. Majumder
  • 2017

A method for generating controlled current waveform through a gated binary clock tree circuit, Indian Patent (IPO), No. 798/KOL/(2014)

  • S. Debnath, B. K. Bhattacharyya, S. Bhowmik
  • 2014
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