A New Algorithm for Post-Silicon Clock Measurement and Tuning

Abstract

The number of speed paths in modern high-performance designs is in the range of millions. Due to unmodelled electrical effects, such as process variations and systemic delay defects, the speed paths are difficult to be measured accurately before the first silicon samples are available. To tolerate these unmodelled electrical effects, clock tuning elements… (More)
DOI: 10.1109/DFT.2011.14

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