A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems

@article{SerranoGotarredona2006ANC,
  title={A Neuromorphic Cortical-Layer Microchip for Spike-Based Event Processing Vision Systems},
  author={Rafael Serrano-Gotarredona and Teresa Serrano-Gotarredona and Antonio Acosta-Jim{\'e}nez and Bernab{\'e} Linares-Barranco},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2006},
  volume={53},
  pages={2548-2566}
}
We present a neuromorphic cortical-layer processing microchip for address event representation (AER) spike-based processing systems. The microchip computes 2-D convolutions of video information represented in AER format in real time. AER, as opposed to conventional frame-based video representation, describes visual information as a sequence of events or spikes in a way similar to biological brains. This format allows for fast information identification and processing, without waiting to process… 
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105 Citations
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105 Citations

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On Real-Time AER 2-D Convolutions Hardware for Neuromorphic Spike-Based Cortical Processing
TLDR
A chip that performs real-time image convolutions with programmable kernels of arbitrary shape is presented, and discussions and results on scaling up the approach for larger pixel arrays and multilayer cortical AER systems are provided.
Fully digital AER convolution chip for vision processing
TLDR
A neuromorphic fully digital convolution microchip for address event representation (AER) spike-based processing systems that computes 2-D convolutions with a programmable kernel in real time.
Performance study of spike visual processing on a Supercomputer: AER-based spike convolution processing on a 320-core cluster
TLDR
A performance study of the CRS supercomputer of the University of Cadiz (UCA) for AER-based convolution processing is presented.
Neocortical frame-free vision sensing and processing through scalable Spiking ConvNet hardware
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern…
FPGA Implementations Comparison of Neuro-cortical Inspired Convolution Processors for Spiking Systems
TLDR
This paper presents two FPGA implementations of AER-based convolution processors that are able to work with 64x64 images and programmable kernels of up to 11x11 elements and the main difference is the use of RAM for integrators in one solution and the absence of Integrators in the second solution that is based on mapping operations.
On scalable spiking convnet hardware for cortex-like visual sensory processing systems
This paper summarizes how Convolutional Neural Networks (ConvNets) can be implemented in hardware using Spiking neural network Address-Event-Representation (AER) technology, for sophisticated pattern…
An AER Spike-Processing Filter Simulator and Automatic VHDL Generator Based on Cellular Automata
TLDR
A software simulator able to gather several spike-based elements into the same workspace in order to test a CA architecture based on AER before a hardware implementation, and produces VHDL for testing the AER-CA into the FPGA of the USBAER A ER-tool.
Advanced Vision Processing Systems: Spike-Based Simulation and Processing
TLDR
This paper presents a simulation AER tool that is developed entirely in Visual C++ 6.0 and can predict the eventual performance of AER-based systems, before the technology becomes mature enough to allow such large systems.
AER Spiking Neuron Computation on GPUs: The Frame-to-AER Generation
TLDR
The first results of a CUDA-based tool focused on the functional processing of AER spikes is presented, with the aim of helping in the design and testing of filters and buses management of these systems.
Fast Pipeline 128×128 pixel spiking convolution core for event-driven vision processing in FPGAs
TLDR
A digital implementation of a parallel and pipelined spiking convolutional neural network (S-ConvNet) core for processing spikes in an event-driven system and results in updating the state of a 128 neuron row in just 12ns.
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