A Networked FPGA-Based Hardware Implementation of a Neural Network Application

@inproceedings{Restrepo2000ANF,
  title={A Networked FPGA-Based Hardware Implementation of a Neural Network Application},
  author={H{\'e}ctor Fabio Restrepo and Ralph Hoffmann and Andr{\'e}s P{\'e}rez-Uribe and Christof Teuscher and Eduardo Sanchez},
  booktitle={FCCM},
  year={2000}
}

• Héctor Fabio Restrepo, Ralph Hoffmann, +2 authors Eduardo Sanchez
• Published in FCCM 2000
• DOI:10.1109/FPGA.2000.903443

This paper describes a networked FPGA-based implementation of the FAST (Flexible Adaptable-Size Topology) architecture, a Arti cial Neural Network (ANN) that dynamically adapts its size. Most ANN models base their ability to adapt to problems on changing the strength of the interconnections between computational elements according to a given learning algorithm. However, constrained interconnection structures may limit such ability. Field programmable hardware devices are very well adapted for… CONTINUE READING

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