A Network Comparison Algorithm for Layout Verification of Integrated Circuits

@article{Barke1984ANC,
  title={A Network Comparison Algorithm for Layout Verification of Integrated Circuits},
  author={Erich Barke},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={1984},
  volume={3},
  pages={135-141}
}
An algorithm is presented which compares the actual topology of an integrated circuit derived from its layout with a user-supplied description of the intended nominal circuit at the transistor level. Devices and nets in both circuits may be named arbitrarily. Using information about device types and pin types to weight the nodes of the corresponding graphs, isomorphism is tested and the names of devices and nets are matched. Differences are isolated and result in an error report for layout… CONTINUE READING