A NOVEL JAVA COPROCESSOR with data hazard handling on FPGA for IC bank card

Abstract

A design of Java coprocessor used in IC bank card is presented in this paper. A 4Kb true dual port SRAM is used for stack to reduce data hazard. Two stack top registers keep same data with the top of stack, which can build a bypass that can handle the data hazard of pipeline. This Java coprocessor can execute 88 Java card instructions, with a size of 8185 gates at a clock of 125MHz.

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Cite this paper

@article{Bai2014ANJ, title={A NOVEL JAVA COPROCESSOR with data hazard handling on FPGA for IC bank card}, author={Yonghong Bai and Liji Wu and Beibei Wang and Xiangmin Zhang}, journal={2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT)}, year={2014}, pages={1-3} }