Corpus ID: 233004448

A Multipurpose Formal RISC-V Specification

@article{Bourgeat2021AMF,
  title={A Multipurpose Formal RISC-V Specification},
  author={Thomas Bourgeat and Ian Clester and Andres Erbsen and Samuel Gruetter and A. Wright and A. Chlipala},
  journal={ArXiv},
  year={2021},
  volume={abs/2104.00762}
}
RISC-V is a relatively new, open instruction set architecture with a mature ecosystem and an official formal machinereadable specification. It is therefore a promising playground for formal-methods research. However, we observe that different formal-methods research projects are interested in different aspects of RISC-V and want to simplify, abstract, approximate, or ignore the other aspects. Often, they also require different encoding styles, resulting in each project starting a new… Expand

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References

SHOWING 1-10 OF 36 REFERENCES
ISA semantics for ARMv8-a, RISC-v, and CHERI-MIPS
TLDR
This paper presents rigorous semantic models for the sequential behaviour of large parts of the mainstream ARMv8-A, RISC-V, and MIPS architectures, and the research CHERI-MIPS architecture, that are complete enough to boot operating systems, variously Linux, FreeBSD, or seL4. Expand
Trustworthy specifications of ARM® v8-A and v8-M system level architecture
  • A. Reid
  • Computer Science
  • 2016 Formal Methods in Computer-Aided Design (FMCAD)
  • 2016
TLDR
This paper describes a 5 year project to change ARM's existing architecture specification process so that machine-readable, executable specifications can be automatically generated from the same materials used to generate ARM's conventional architecture documentation. Expand
Integration verification across software and hardware for a simple embedded system
TLDR
This work reports on the first verification of a realistic embedded system, with its application software, device drivers, compiler, and RISC-V processor represented inside the Coq proof assistant as one mathematical object, with a machine-checked proof of functional correctness. Expand
The bedrock structured programming system: combining generative metaprogramming and hoare logic in an extensible program verifier
TLDR
The design and implementation of an extensible programming language and its intrinsic support for formal verification, based on a cross-platform core combining characteristics of assembly languages and compiler intermediate languages, and an expressive notion of certified low-level macros are introduced. Expand
Kami: a platform for high-level parametric hardware specification and its modular verification
TLDR
Kami is introduced, a Coq library that enables similar expressive and modular reasoning for hardware designs expressed in the style of the Bluespec language, and can specify, implement, and verify realistic designs entirely within Coq, ending with automatic extraction into a pipeline that bottoms out in FPGAs. Expand
The semantics of x86-CC multiprocessor machine code
TLDR
This work develops a rigorous and accurate semantics for x86 multiprocessor programs, from instruction decoding to relaxed memory model, mechanised in HOL, and contrast the x86 model with some aspects of Power and ARM behaviour. Expand
Ready, set, verify! applying hs-to-coq to real-world Haskell code (experience report)
TLDR
HS-to-coq is used to translate significant portions of Haskell’s containers library into Coq, and verify it against specifications that it is feasible to verify mature, widely-used, highly optimized, and unmodified Haskell code. Expand
A Trustworthy Monadic Formalization of the ARMv7 Instruction Set Architecture
TLDR
A novel and efficient testing approach has been developed, based on automated forward proof and communication with ARM development boards, and some details of the endeavours that have been made to ensure that the sizeable model is valid and trustworthy are given. Expand
Verified compilation on a verified processor
TLDR
This paper shows how to extend the trustworthy development methodology of the CakeML project, including its verified compiler, with a connection to verified hardware, and results are an approach to producing verified stacks that scales to proving correctness, at the hardware level, of the execution of realistic software including compilers and proof checkers. Expand
Directions in ISA Specification
TLDR
This rough diamond presents a new domain-specific language (DSL) for producing detailed models of Instruction Set Architectures, such as ARM and x86, with an ARMv7 model used as a case study. Expand
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