A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers

@article{Wu2014AMP,
  title={A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers},
  author={Jianhui Wu and Jiafeng Zhu and YingCheng Xia and Na Bai},
  journal={IEEE Transactions on Circuits and Systems II: Express Briefs},
  year={2014},
  volume={61},
  pages={264-268}
}
A multiple-stage parallel replica-bitline (RBL) delay addition technique for reducing the timing variation of static random access memory (SRAM) sense amplifiers (SAs) is proposed. Multiple-stage RBLs with a sufficient count of replica cells are utilized in parallel. Subsequently, the RBL delay of each stage is digitized and added together by the proposed timing addition circuit to the target timing for SAs. Compared with existing techniques, the proposed technique can achieve lower timing… CONTINUE READING
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