A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package

@article{Pulici2008AMI,
  title={A Modified IBIS Model Aimed at Signal Integrity Analysis of Systems in Package},
  author={Paolo Pulici and Antonio Girardi and Gian Pietro Vanalli and Roberto Izzi and Giacomo Bernardi and Giancarlo Ripamonti and Antonio Giuseppe Maria Strollo and Giovanni Campardo},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2008},
  volume={55},
  pages={1921-1928}
}
Input-output buffer information specification BIS (IBIS) models are descriptions of the output buffers, used by the printed circuit board (PCB) designer to evaluate the integrity and the quality of the signals. The extension of the use of IBIS models to the system in package (SiP) world is considered. It is found that IBIS models demonstrate some limits for this application, mainly due to the poor stabilization of the supply voltage rails. An example highlighting the IBIS model limits is given… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-10 OF 12 CITATIONS

IBIS model formulation and extraction for SPI evaluation

  • 2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)
  • 2015
VIEW 6 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

0 Behavioral Modeling of Flash Memories

VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

New Multiport I/O Model for Power-Aware Signal Integrity Analysis

  • IEEE Transactions on Components, Packaging and Manufacturing Technology
  • 2016
VIEW 3 EXCERPTS
CITES METHODS & BACKGROUND
HIGHLY INFLUENCED

Behavioral Modeling of Flash Memories

VIEW 4 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

Power integrity design for package-board system based on BGA

  • 2017 18th International Conference on Electronic Packaging Technology (ICEPT)
  • 2017
VIEW 1 EXCERPT
CITES BACKGROUND

An embedded multimedia communication terminal based on DSP+FPGA

  • Multimedia Tools and Applications
  • 2016
VIEW 1 EXCERPT
CITES METHODS

A complete solution for Board-Level Signal Integrity Analysis Using IBIS Models

  • 2013 13th Mediterranean Microwave Symposium (MMS)
  • 2013
VIEW 1 EXCERPT
CITES BACKGROUND

References

Publications referenced by this paper.
SHOWING 1-10 OF 11 REFERENCES

A Reduced Output Ringing CMOS Buffer

  • IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2007
VIEW 1 EXCERPT

Interconnections effects on package on package design

P. Pulici
  • Proc. Signal Propagat. Interconnects Conf., 2007, pp. 163–166.
  • 2007
VIEW 1 EXCERPT

1 Gb stacked solution of multilevel NOR flash memory packaged in a LFBGA 8 mm by 10 mm by 1.4 mm of thickness

  • EuroSime 2006 - 7th International Conference on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems
  • 2006

Fully testable double stacked logic plus flash with embedded connections

G. Vanalli
  • Proc. IMAPS Electron. Packag. Conf., Tampere, Finland, 2004, pp. 183–187.
  • 2004
VIEW 1 EXCERPT

SSN issues with IBIS models

  • Electrical Performance of Electronic Packaging - 2004
  • 2004
VIEW 1 EXCERPT

SPICE and IBIS modeling kits the basis for signal integrity analyses

  • Proceedings of Symposium on Electromagnetic Compatibility
  • 1996
VIEW 1 EXCERPT

Bakoglu, Circuits, Interconnections and Packaging for VLSI

H B.
  • 1990
VIEW 2 EXCERPTS

Similar Papers

Loading similar papers…