• Corpus ID: 227334386

A Modern Primer on Processing in Memory

@article{Mutlu2020AMP,
  title={A Modern Primer on Processing in Memory},
  author={Onur Mutlu and Saugata Ghose and Juan G'omez-Luna and Rachata Ausavarungnirun},
  journal={ArXiv},
  year={2020},
  volume={abs/2012.03112}
}
Modern computing systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) data… 

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References

SHOWING 1-10 OF 455 REFERENCES

D-RaNGe: Using Commodity DRAM Devices to Generate True Random Numbers with Low Latency and High Throughput

D-RanGe is a methodology for extracting true random numbers from commodity DRAM devices with high throughput and low latency by deliberately violating the read access timing parameters and is evaluated using the commonly-used NIST statistical test suite for randomness.

The DRAM Latency PUF: Quickly Evaluating Physical Unclonable Functions by Exploiting the Latency-Reliability Tradeoff in Modern Commodity DRAM Devices

The DRAM latency PUF is introduced, a new class of fast, reliable DRAM PUFs that satisfy runtime-accessible PUF requirements and are quickly generated irrespective of operating temperature using a real system with no additional hardware modications.

Low-Cost Inter-Linked Subarrays (LISA): Enabling fast inter-subarray data movement in DRAM

A new DRAM substrate, Low-Cost Inter-Linked Subarrays (LISA), whose goal is to enable fast and efficient data movement across a large range of memory at low cost, and whose combined benefit is higher than the benefit of each alone, on a variety of workloads and system configurations.

PIM-enabled instructions: A low-overhead, locality-aware processing-in-memory architecture

A new PIM architecture is proposed that does not change the existing sequential programming models and automatically decides whether to execute PIM operations in memory or processors depending on the locality of data, and combines the best parts of conventional and PlM architectures by adapting to data locality of applications.

ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs

This work is the first work to demonstrate in-memory computation with off-the-shelf, unmodified, commercial, DRAM, by violating the nominal timing specification and activating multiple rows in rapid succession, which happens to leave multiple rows open simultaneously, thereby enabling bit-line charge sharing.

MAGIC—Memristor-Aided Logic

In this brief, a memristor-only logic family, i.e., memristar-aided logic (MAGIC), is presented, and in each MAGIC logic gate, memristors serve as an input with previously stored data, and an additional Memristor serves as an output.

Memristor-based IMPLY logic design procedure

The design and behavior of a memristive-based logic gate - an IMPLY gate - are presented and design issues such as the tradeoff between speed (fast write times) and correct logic behavior are described, as part of an overall design methodology.

Memristor-Based Material Implication (IMPLY) Logic: Design Principles and Methodologies

The IMPLY logic gate, a memristor-based logic circuit, is described and a methodology for designing this logic family is proposed, based on a general design flow suitable for all deterministic memristive logic families.

Simultaneous Multi-Layer Access: Improving 3D-Stacked Memory Bandwidth at Low Cost

  • TACO
  • 2016

Exploiting Near-Data Processing to Accelerate Time Series Analysis

A time series is a chronologically ordered set of samples of a real-valued variable that can contain millions of observations. Time series analysis is used to analyze information in a wide variety of
...