A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET

@article{Jaiswal2018AMF,
  title={A Model for Gate-Underlap-Dependent Short- Channel Effects in Junctionless MOSFET},
  author={Nivedita Jaiswal and Abhinav Kranti},
  journal={IEEE Transactions on Electron Devices},
  year={2018},
  volume={65},
  pages={881-887}
}
In this paper, we investigate the impact of gate–source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or… CONTINUE READING