A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages

@article{Syed2007AMF,
  title={A Methodology for Drop Performance Modeling and Application for Design Optimization of Chip-Scale Packages},
  author={Ahmer Syed and Seung Mo Kim and Wei Hua Lin and Jin Young Kim and Eun Sook Sohn and Jae Hyeon Shin},
  journal={IEEE Transactions on Electronics Packaging Manufacturing},
  year={2007},
  volume={30},
  pages={42-48}
}
As handheld electronic products are more prone to being dropped during useful life, package-to-board interconnect reliability has become a major concern for these products. This has prompted the industry to evaluate the drop performance of chip-scale packages (CSPs) while mounted on printed wiring boards using board-level drop testing. Although a new board-level test method has been standardized through JEDEC (JESD22-B111), characterization tests take quite a long time to complete, extending… CONTINUE READING

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