## An algorithm to find optimum support-reducing decompositions for index generation functions

- Tsutomu Sasao, Kyu Matsuura, Yukihiro Iguchi
- Design, Automation & Test in Europe Conference…
- 2017

1 Excerpt

- Published 2015 in IEICE Transactions

In the era of IPv6, since the number of IPv6 addresses rapidly increases and the required speed is more than Giga lookups per second (GLPS), an area-efficient and high-speed IP lookup architecture is desired. This paper shows a parallel index generation unit (IGU) for memorybased IPv6 lookup architecture. To reduce the size of memory in the IGU, we use a linear transformation and a row-shift decomposition. A singlememory realization requires O(2l log k) memory size, where l denotes the length of prefix, while the realization using IGU requires O(kl) memory size, where k denotes the number of prefixes. In IPv6 prefix lookup, since l is at most 64 and k is about 340 K, the IGU drastically reduces the memory size. Also, to reduce the cost, we realize the parallel IGU by using both onchip and off-chip memories. We show a design algorithm for the parallel IGU to store given off-chip and on-chip memories. The parallel IGU has a simple architecture and performs lookup by using complete pipelines those insert the pipeline registers in all the paths. We loaded more than 340 K IPv6 pseudo prefixes on the Xilinx Virtex 6 FPGA with off-chip DDRII+ Static RAMs (SRAMs). Its lookup speed is 1.100 giga lookups per second (GLPS) which is sufficient for the required speed for a next generation 400 Gbps link throughput. As for the normalized area and lookup speed, our implementation outperforms existing FPGA implementations. key words: CAM, IP lookup, index generation unit, FPGA

@article{Nakahara2015AMI,
title={A Memory-Based IPv6 Lookup Architecture Using Parallel Index Generation Units},
author={Hiroki Nakahara and Tsutomu Sasao and Munehiro Matsuura and Hisashi Iwamoto and Yasuhiro Terao},
journal={IEICE Transactions},
year={2015},
volume={98-D},
pages={262-271}
}