A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance

@article{Myjak2008AMR,
  title={A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance},
  author={Mitchell J. Myjak and Jos{\'e} G. Delgado-Frias},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2008},
  volume={16},
  pages={14-23}
}
Reconfigurable hardware has become a well-accepted option for implementing digital signal processing (DSP). Traditional devices such as field-programmable gate arrays offer good fine-grain flexibility. More recent coarse-grain reconfigurable architectures are optimized for word-length computations. We have developed a medium-grain reconfigurable architecture that combines the advantages of both approaches. Modules such as multipliers and adders are mapped onto blocks of 4-bit cells. Each cell… CONTINUE READING

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