Corpus ID: 18490824


  author={Jos{\'e} G. Delgado-Frias and Mitchell J. Myjak and Fredrick L. Anderson and Daniel R. Blum},
Digital signal processing (DSP) is an essential component of many applications, including multimedia and communications systems. The recent surge in wireless and mobile computing underscores the need for high-performance low power DSP hardware. Reconfigurable hardware balances these requirements with development costs by providing system designers a viable alternative to custom integrated circuits. This paper describes a novel reconfigurable architecture for DSP applications. The device… 
A Two-Level Reconfigurable Architecture for Digital Signal Processing
This paper describes a novel reconfigurable architecture for digital signal processing (DSP) that combines the flexibility of memory elements with the speed of DOMINO logic.
H-tree based configuration schemes for a reconfigurable DSP architecture
Two efficient configuration schemes for a reconfigurable DSP hardware that utilizes an H-tree interconnection network to link clusters of logic blocks, or cells, to map the desired circuits are described.
An experimental analysis of a new mixed grain-based dynamically reconfigurable architecture
  • L. Sterpone
  • Computer Science
    2006 13th IEEE International Conference on Electronics, Circuits and Systems
  • 2006
The experimental results gathered through an accurate simulation model of ReCoM show performance figures encouragingly better than other DSP or alternative reconfigurable systems and demonstrate that Re coCoM is very scalable and it successfully extracts the parallelism from streamed applications.
A high-performance unicast configuration scheme for an H-tree based reconfigurable hardware
An efficient configuration scheme for a reconfigurable DSP hardware that utilizes a hierarchical interconnection network to link clusters of logic blocks, or cells, to map the desired circuits.
ReCoM: A new Reconfigurable Compute Fabric Architecture for Computation-Intensive Applications
  • L. Sterpone, M. Violante
  • Computer Science
    2006 IEEE Design and Diagnostics of Electronic Circuits and systems
  • 2006
The ReCoM architecture is described and its effectiveness for a digital signal processing benchmark application and its efficient configuration and data memory architecture is presented.
An Embedded Reconfigurable IP Core with Variable Grain Logic Cell Architecture
This paper proposes a variable grain logic cell (VGLC) architecture, which consists of a 4-bit ripple carry adder with configuration memory bits and develops a technology mapping tool, which improves logic depth and reduces the number of configuration data by 55% on average, as compared to the Virtex-4 logic cell architecture.
A Reconfigurable Architecture of Software-Defined-Radio for Wireless Local Area Networks
The Software-Defined-Radio (SDR) project at the University of Twente aims at combining two different WLAN standards, Bluetooth and HiperLAN2, on one common flexible hardware platform. A functional
Enhanced fault-tolerant CMOS memory elements
CMOS memory elements used in space as well as some terrestrial applications must be immune to radiation-induced errors such as single event upsets. Existing designs protect the stored data against


A reconfigurable function array architecture for 3G and 4G wireless terminals
An application domain specific architecture for the digital signal-processing domain was conceived and the Field Programmable Function Array (FPFA) was conceived, a reconfigurable device with a data-path that can be configured to implement a number of DSP algorithms energy efficiently.
Reconfigurable Computing for Digital Signal Processing: A Survey
It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential.
Configurable Logic for Digital Signal Processing April 28 , 1999
The software programmable digital signal processor (DSP) has been the cornerstone of commercial configurable signal processing hardware for approximately 16 years. In comparatively recent times,
Configurable Processors for Embedded Computing
Ever-increasing chip capacities have given rise to configurable processors that offer virtually unlimited choices in core architectures.
Low cost & fast turnaround: reconfigurable Graph-Based execution units
New devices with the efficiency of full-custom designs and the programmability of FPGAs will ease many aspects of the design of complex systems, without the high cost of mask production. The
Coarse grain reconfigurable architectures
  • R. Hartenstein
  • Computer Science
    Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
  • 2001
The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of
On-line error detection and correction in storage elements with cross-parity check
The cross-parity check is proposed as a method for an on-line detection of multiple bit-errors in storage elements of microprocessors like registers or register files, which can be performed by software routines or additional hardware.
Environment for implementing DSP algorithms in reconfigurable hardware
  • Proc. High Performance Embedded Computing Workshop (HPEC),
  • 2000
and A
  • M. Reza, Configurable logic for digital signal processing
  • 1999