Corpus ID: 18490824

A MEDIUM-GRAIN RECONFIGURABLE CELL ARRAY FOR DSP

@inproceedings{DelgadoFrias2003AMR,
  title={A MEDIUM-GRAIN RECONFIGURABLE CELL ARRAY FOR DSP},
  author={Jos{\'e} G. Delgado-Frias and Mitchell J. Myjak and Fredrick L. Anderson and Daniel R. Blum},
  year={2003}
}
Digital signal processing (DSP) is an essential component of many applications, including multimedia and communications systems. The recent surge in wireless and mobile computing underscores the need for high-performance low power DSP hardware. Reconfigurable hardware balances these requirements with development costs by providing system designers a viable alternative to custom integrated circuits. This paper describes a novel reconfigurable architecture for DSP applications. The device… 
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References

SHOWING 1-9 OF 9 REFERENCES
A reconfigurable function array architecture for 3G and 4G wireless terminals
TLDR
An application domain specific architecture for the digital signal-processing domain was conceived and the Field Programmable Function Array (FPFA) was conceived, a reconfigurable device with a data-path that can be configured to implement a number of DSP algorithms energy efficiently.
Reconfigurable Computing for Digital Signal Processing: A Survey
TLDR
It is shown that while contemporary reconfigurable computing can be applied to a variety of DSP applications including video, audio, speech, and control, much work remains to realize its full potential.
Configurable Logic for Digital Signal Processing April 28 , 1999
The software programmable digital signal processor (DSP) has been the cornerstone of commercial configurable signal processing hardware for approximately 16 years. In comparatively recent times,
Configurable Processors for Embedded Computing
TLDR
Ever-increasing chip capacities have given rise to configurable processors that offer virtually unlimited choices in core architectures.
Low cost & fast turnaround: reconfigurable Graph-Based execution units
New devices with the efficiency of full-custom designs and the programmability of FPGAs will ease many aspects of the design of complex systems, without the high cost of mask production. The
Coarse grain reconfigurable architectures
  • R. Hartenstein
  • Computer Science
    Proceedings of the ASP-DAC 2001. Asia and South Pacific Design Automation Conference 2001 (Cat. No.01EX455)
  • 2001
The paper gives a brief survey over a decade of R&D on coarse grain reconfigurable hardware and related compilation techniques and points out its significance to the emerging discipline of
On-line error detection and correction in storage elements with cross-parity check
TLDR
The cross-parity check is proposed as a method for an on-line detection of multiple bit-errors in storage elements of microprocessors like registers or register files, which can be performed by software routines or additional hardware.
Environment for implementing DSP algorithms in reconfigurable hardware
  • Proc. High Performance Embedded Computing Workshop (HPEC),
  • 2000
and A
  • M. Reza, Configurable logic for digital signal processing
  • 1999