A Low-leakage Current Power 45-nm CMOS SRAM

  title={A Low-leakage Current Power 45-nm CMOS SRAM},
  author={Shyam Akashe and Deepak Kumar Sinha and Sanjay Sharma},
  journal={Indian journal of science and technology},
A low leakage power, 45-nm 1Kb SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area. 

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