A Low-leakage Current Power 45-nm CMOS SRAM

@article{Akashe2011ALC,
  title={A Low-leakage Current Power 45-nm CMOS SRAM},
  author={Shyam Akashe and Deepak Kumar Sinha and Sanjay Sharma},
  journal={Indian journal of science and technology},
  year={2011},
  volume={4},
  pages={440-442}
}
A low leakage power, 45-nm 1Kb SRAM was fabricated. The stand-by leakage power of a 1K-bit memory cell array incorporating a newly-developed leakage current reduction circuit called a self-controllable voltage level (SVL) circuit was only 3.7 nW, which is 5.4% that of an equivalent conventional memory-cell array at a VDD of 1.8V. On the other hand, the speed remained almost constant with a minimal overhead in terms of the memory cell array area. 

Figures and Tables from this paper

A Survey on the Performance Analysis of FinFET SRAM Cells for Different Technologies
  • Girish
  • Engineering, Computer Science
  • 2015
TLDR
Comparison of conventional CMOS, Independent-Gate (IG) and Tied Gate (TG) FinFET SRAM standard cells performance analysis is done with respect to leakage power, Static Noise Margin (SNM) and delay.
Optimization of Leakage Current in SRAM Cell Using Shorted Gate DG FinFET
TLDR
The total leakage of DG FinFET SRAM cell is reduced by 34% after applying self controllable voltage level technique and the sub-threshold leakage current and gate leakage current of internal transistors are observed.
Low Power Memristor Based 7T SRAM Using MTCMOS Technique
  • Vijay Singh Baghel, S. Akashe
  • Engineering, Computer Science
    2015 Fifth International Conference on Advanced Computing & Communication Technologies
  • 2015
TLDR
7T simple SRAM and technique based 7T SRAM has been designed and parameters like total power and leakage power has been calculated and MTCMOS (Multi Threshold CMOS) technique is used, it is a power reducing technique that helps in reducing leakage power in the SRAM by turning of the inactive circuit domains.
Design and Performance Estimation of low Power Frequency Divider in 45nm CMOS Technology
paper presents a low power low voltage CMOS frequency divider using power gating technique, that's why it reduces the overall power consumption of circuit and increases the efficiency of circuit.
Analysis and design of low power SRAM cell using independent gate FinFET
TLDR
A six transistor SRAM cell based on independent-gate FinFET technology is described in this paper for simultaneously reducing the active and standby mode power consumption.
Design and Implementation of Sequential Circuit Based On Low Power Using 45nm Technology
  • Engineering, Computer Science
  • 2019
A low power voltage CMOS frequency divider using power gating technique, that’s why it reduces the overall power consumption of circuit and increases the efficiency of circuit. .A memory element
A New Approach for Low Power Decoder for Memory Array
TLDR
This work studies the location decoder for SRAM memory, focusing on deferral streamlining and control effective circuit systems and Modified hybrid type of decoding topology is illustrated and it is compared with traditional type decoders which include both static and dynamic types using 180 nm CMOS technology in Cadence Virtuoso environment.
Development of 3T eDRAM gain cells for enhancing read margin and data retention
This paper presents three transistors (3T) based Dynamic Random Access Memory (DRAM) cell in which noise, static power, and data retention voltage (DRV) have been reduced. The spesified parameters in
Implementation of 5–32 address decoders for SRAM memory in 180nm technology
  • B. N. Bagamma, K. V. Patel, Prasad Ravi
  • Computer Science
    2017 International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)
  • 2017
TLDR
An efficient and modified address decoding topology is implemented which counts the least number of transistors in order to reduce the range of SRAM using only one 2–4 decoder, 3–8 decoder and row decoder in CMOS 180nm technology using cadence virtuoso tool, and is compared with different types of decoders.
Implementation of Low Power Flip Flop Design in Nanometer Regime
TLDR
This paper has illustrated Single Edge Triggered 5T Delay flip flop design with leakage reduction technique in which the feedback path get removed that was present in the conventional Delay Flip Flop design, and shows a tremendous reduction in leakage power nearly by 68% at 1volt supply in comparison with the conventional Set-Reset latch based DFF.
...
...

References

SHOWING 1-3 OF 3 REFERENCES
Driving source-line cell architecture for sub-1-V high-speed low-power applications
TLDR
A novel SRAM cell architecture for sub-1-V high-speed operation is proposed that uses neither low-V/sub th/ MOSFETs nor modified cell layout patterns, and the achievability of low-power 100-MHz operation over a wide range of supply voltages is demonstrated.