A Low-Power Multi-Pin Maze Routing Methodology

Abstract

As VLSI technologies scale into the deep submicron (DSM) realm, the minimum feature size continues to shrink. In contrast, the average die size is expected to remain constant or to slightly increase with each technology generation. This results in an average increase in the global interconnect lengths. In order to mitigate the impact of these global wires… (More)
DOI: 10.1109/ISQED.2007.15

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