A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques

@article{Honda2007ALL,
  title={A Low-Power Low-Voltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance Coupling Techniques},
  author={Keishi Honda and Masanori Furuta and Shoji Kawahito},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={757-765}
}
This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample-and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode amplifier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power… CONTINUE READING

Citations

Publications citing this paper.
SHOWING 1-10 OF 20 CITATIONS

Split-based 200Msps and 12 bit ADC design

  • 2015 IEEE 11th International Conference on ASIC (ASICON)
  • 2015
VIEW 5 EXCERPTS
CITES BACKGROUND
HIGHLY INFLUENCED

Power Dissipation Bounds for High-Speed Nyquist Analog-to-Digital Converters

  • IEEE Transactions on Circuits and Systems I: Regular Papers
  • 2009
VIEW 9 EXCERPTS
CITES BACKGROUND & METHODS
HIGHLY INFLUENCED

A 7-bit 26-MS/s SAR ADC in 0.18 μm CMOS process for WSN application

  • 2012 4th International High Speed Intelligent Communication Forum
  • 2012
VIEW 3 EXCERPTS
CITES METHODS & BACKGROUND
HIGHLY INFLUENCED

A 300MHz 10b time-interleaved pipelined-SAR ADC

  • 2013 IEEE 10th International Conference on ASIC
  • 2013

A 2.3mW 10-bit 170MS/s two-step binary-search assisted time-interleaved SAR ADC

  • Proceedings of the IEEE 2012 Custom Integrated Circuits Conference
  • 2012
VIEW 1 EXCERPT
CITES BACKGROUND

State-of-the-art pipeline A/D converter survey and analysis

  • 2012 International Conference on Informatics, Electronics & Vision (ICIEV)
  • 2012

References

Publications referenced by this paper.
SHOWING 1-10 OF 16 REFERENCES

A 1 V 30 mW 10 bit 100 MSample/s pipeline A/D converter using capacitance coupling techniques

K. Honda, M. Furuta, S. Kawahito
  • Symp. VLSI Circuits 2006 Dig. Tech. Papers, Jun. 2006, pp. 276–277.
  • 2006
VIEW 1 EXCERPT

Low-Power Design of Pipeline A/D Converters

  • IEEE Custom Integrated Circuits Conference 2006
  • 2006
VIEW 1 EXCERPT

A 3.3 mW 12 MS/s 10b pipelined ADC in 90 nm digital CMOS

  • ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005.
  • 2005
VIEW 2 EXCERPTS

A 1.2 V 220 MS/s 10 bit pipeline ADC implemented in 0.13 m digital CMOS

B. Hernes, A. Briskemyr, +3 authors Ø. Moldsvor
  • IEEE ISSCC 2004 Dig. Tech. Papers, Feb. 2004, pp. 256–257.
  • 2004

A pseudo-class-AB telescopic-cascode operational amplifier

  • 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512)
  • 2004
VIEW 1 EXCERPT

A 75mW 10bit 120MSample/s parallel pipeline ADC

  • ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705)
  • 2003
VIEW 1 EXCERPT

A 16 mW 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture

  • 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)
  • 2002

Similar Papers