A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit

@article{Wattanapanitch2011AL3,
  title={A Low-Power 32-Channel Digitally Programmable Neural Recording Integrated Circuit},
  author={Woradorn Wattanapanitch and R. Sarpeshkar},
  journal={IEEE Transactions on Biomedical Circuits and Systems},
  year={2011},
  volume={5},
  pages={592-602}
}
  • Woradorn Wattanapanitch, R. Sarpeshkar
  • Published 2011
  • Engineering, Medicine, Computer Science
  • IEEE Transactions on Biomedical Circuits and Systems
  • We report the design of an ultra-low-power 32-channel neural-recording integrated circuit (chip) in a 0.18 μ m CMOS technology. The chip consists of eight neural recording modules where each module contains four neural amplifiers, an analog multiplexer, an A/D converter, and a serial programming interface. Each amplifier can be programmed to record either spikes or LFPs with a programmable gain from 49-66 dB. To minimize the total power consumption, an adaptive-biasing scheme is utilized to… CONTINUE READING
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