A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion

@article{Chen2009AL2,
  title={A Low-Power 2.4-GHz CMOS GFSK Transceiver With a Digital Demodulator Using Time-to-Digital Conversion},
  author={Chia-Pei Chen and Ming-Jen Yang and Hsun-Hsiu Huang and Tung-Ying Chiang and Jheng-Liang Chen and Ming-Chieh Chen and Kuei-Ann Wen},
  journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
  year={2009},
  volume={56},
  pages={2738-2748}
}
A technique of time-to-digital conversion is utilized in a digital demodulator for a low-power 2.4-GHz CMOS GFSK transceiver. The proposed time-to-digital converter (TDC) employs a self-sampling technique and an auto-calibration algorithm to avoid edge synchronization problems and the need of a delay-locked loop (DLL). With the TDC, a limiter and a digital demodulator can be employed simultaneously in the receiver to achieve low power consumption and high performance. Additionally, in the… CONTINUE READING
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