## Dynamic Element Matching Techniques for Static and Dynamic Errors in Continuous-Time Multi-Bit ΔΣ Modulators

- Arindam Sanyal, Nan Sun
- IEEE J. Emerg. Sel. Topics Circuits Syst.
- 2015

- Published 1996

Delta-sigma ( ) analog-to-digital converters (ADC’s) rely on oversampling to achieve high-resolution. By applying multibit quantization to overcom stability limitations, a circuit topology with greatly reduced oversampling requirements is developed. A 14-bit 500-kHz ADC is described that uses an oversampling ratio of only 16. A fourth-order embedded modulator, four-bit quantizer, and self-calibrated digital-to-analog converter (DAC) are used to achieve this performance. Although the high-order embedded architecture was previously thought to be unstable, it is shown that with proper design, a robust system can be obtained. Circuit design and implementation in a 1.2m CMOS process are presented. Experimental results give a dynamic range of 84 dB with a sampling rate of 8 MHz and oversampling ratio of 16. This is the lowest oversampling ratio for this resolution and bandwidth achieved to date.

@inproceedings{Baird1996ALO,
title={A Low Oversampling Ratio 14-b 500-kHz ADC with a Self-Calibrated Multibit DAC},
author={Rex T. Baird and Terri S. Fiez},
year={1996}
}