A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips

@article{Fattah2015ALF,
  title={A Low-Overhead, Fully-Distributed, Guaranteed-Delivery Routing Algorithm for Faulty Network-on-Chips},
  author={Mohammad Fattah and Antti Airola and Rachata Ausavarungnirun and Nima Mirzaei and Pasi Liljeberg and Juha Plosila and Siamak Mohammadi and Tapio Pahikkala and Onur Mutlu and Hannu Tenhunen},
  journal={Proceedings of the 9th International Symposium on Networks-on-Chip},
  year={2015}
}
This paper introduces a new, practical routing algorithm, Maze-routing, to tolerate faults in network-on-chips. The algorithm is the first to provide all of the following properties at the same time: 1) fully-distributed with no centralized component, 2) guaranteed delivery (it guarantees to deliver packets when a path exists between nodes, or otherwise indicate that destination is unreachable, while being deadlock and livelock free), 3) low area cost, 4) low reconfiguration overhead upon a… Expand
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References

SHOWING 1-10 OF 50 REFERENCES
Fault-tolerant routing for on-chip network without using virtual channels
TLDR
By constructing an acyclic channel dependency graph that breaks all cycles and preserves connectivity of the network, this work proposes a new deadlock-free fault-tolerant adaptive routing without virtual channel. Expand
Topology-agnostic fault-tolerant NoC routing method
TLDR
Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers, demonstrating that the proposed method may be adopted in NoC designs. Expand
Immunet: a cheap and robust fault-tolerant packet routing mechanism
TLDR
A new and efficient mechanism to tolerate failures in interconnection networks for parallel and distributed computers, denoted as Immunet, is presented, which automatically reacts with a hardware reconfiguration of the surviving network resources in the presence of failures. Expand
An Efficient Implementation of Distributed Routing Algorithms for NoCs
TLDR
LBDR (logic-based distributed routing) is proposed as a new routing method that removes the need of using routing tables at all and enables the implementation of many routing algorithms on most of the practical topologies in a multi-core system. Expand
Evaluation of on-chip networks using deflection routing
TLDR
This paper evaluates deflection networks with different topologies such as mesh, torus and Manhattan Street Network, different routing algorithms such as random, dimension XY, delta XY and minimum deflection, as well as different deflection policies such as non-priority, weighted priority and straight-through policies, suggesting that the performance of a deflection network is more sensitive to its topology than the other two parameters. Expand
d2-LBDR: Distance-driven routing to handle permanent failures in 2D mesh NoCs
With the advent of deep sub-micron technology, fault-tolerant solutions are needed to keep many-core chips operative. In NoCs, Logic Based Distributed Routing (LBDR) proved to be a flexible routingExpand
A case for bufferless routing in on-chip networks
TLDR
A case is made for a new approach to designing on-chip interconnection networks that eliminates the need for buffers for routing or flow control and new algorithms for routing without using buffers in router input/output ports are described. Expand
Routing with guaranteed delivery in ad hoc wireless networks
TLDR
The first distributed algorithms for routing that do not require duplication of packets or memory at the nodes and yet guarantee that a packet is delivered to its destination are described. Expand
On delivery guarantees of face and combined greedy-face routing in ad hoc and sensor networks
TLDR
This article gives the first complete and formal proofs that several proposed face routing, and combined greedy-face routing schemes do guarantee delivery in specific graph classes or even any arbitrary planar graphs. Expand
MinBD: Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect
TLDR
This work proposes a new NoC router design called the minimally-buffered deflection (MinBD) router, which combines deflection routing with a small "side buffer," which is much smaller than conventional input buffers, and is more energy efficient than all prior designs. Expand
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