A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution

@article{Lee2009ALW,
  title={A Low-Noise Wideband Digital Phase-Locked Loop Based on a Coarse–Fine Time-to-Digital Converter With Subpicosecond Resolution},
  author={Minjae Lee and M. Heidari and A. A. Abidi},
  journal={IEEE Journal of Solid-State Circuits},
  year={2009},
  volume={44},
  pages={2808-2816}
}
This paper presents the design of a digital PLL which uses a high-resolution time-to-digital converter (TDC) for wide loop bandwidth. The TDC uses a time amplification technique to reduce the quantization noise down to less than 1 ps root mean square (RMS). Additionally TDC input commutation reduces low-frequency spurs due to inaccurate TDC scaling factor in a counter-assisted digital PLL. The loop bandwidth is set to 400 kHz with a 25 MHz reference. The in-band phase noise contribution from… CONTINUE READING
Highly Cited
This paper has 95 citations. REVIEW CITATIONS