A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology

@article{Chaturvedi2011ALL,
  title={A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology},
  author={Vikram Chaturvedi and B. Amrutur},
  journal={2011 24th Internatioal Conference on VLSI Design},
  year={2011},
  pages={328-333}
}
  • Vikram Chaturvedi, B. Amrutur
  • Published 2011
  • Engineering, Computer Science
  • 2011 24th Internatioal Conference on VLSI Design
  • Chronic recording of neural signals is indispensable in designing efficient brain machine interfaces and in elucidating human neurophysiology. [...] Key Method It can be biased adaptively from 200 nA to 2 uA, modulating input referred noise from 9.92 uV to 3.9 uV. We also describe a low noise design technique which minimizes the noise contribution of the load circuitry. The amplifier can pass signal from 5 Hz to 7 kHz while rejecting input DC offsets at electrode-electrolyte interface.Expand Abstract
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