A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS

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@article{Shabany2013ALL, title={A Low-Latency Low-Power QR-Decomposition ASIC Implementation in 0.13 µm CMOS}, author={Mahdi Shabany and Dimpesh Patel and P. Glenn Gulak}, journal={IEEE Trans. on Circuits and Systems}, year={2013}, volume={60-I}, pages={327-340} }