A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications

Abstract

This paper describes a wide-range programmable frequency synthesizer building block for 4.25Gbps serial link applications. A unique feature of the design is the use of variable gain charge pumps to adjust loop gain as well as damping in order to minimize output jitter. The synthesizer architecture includes pre and post dividers to maximize programmability. A novel implementation of the high speed divide circuit is also described.

DOI: 10.1109/SOCC.2005.1554443

Cite this paper

@inproceedings{Kelkar2005ALJ, title={A Low Jitter Programmable Frequency Synthesizer for 4.25Gbps Serial Link Applications}, author={Ram Kelkar and Dave Flye and Anjali Malladi and Joseph Natonio and Chri Scoville and Ken Short and Pradeep Thiagarajan}, booktitle={SoCC}, year={2005} }