A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

@article{Hsu2011ALA,
  title={A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme},
  author={Hsuan-Jung Hsu and Shi-Yu Huang},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2011},
  volume={19},
  pages={165-170}
}
In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of the digitally controlled oscillator (DCO) so as to further reduce the phase error and jitter… CONTINUE READING
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References

Publications referenced by this paper.
Showing 1-10 of 12 references

A high-resolution all-digital phase-locked loop with its application to built-in speed grading for memory

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT) • 2008
View 8 Excerpts

All-Digital PLL With Ultra Fast Settling

IEEE Transactions on Circuits and Systems II: Express Briefs • 2007
View 2 Excerpts

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

IEEE Transactions on Circuits and Systems II: Express Briefs • 2007
View 2 Excerpts

An All-Digital Phase-Locked Loop with High-Resolution for SoC Applications

2006 International Symposium on VLSI Design, Automation and Test • 2006
View 3 Excerpts

A self-biased PLL with current-mode filter for clock generation

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005. • 2005
View 1 Excerpt

A digitally controlled PLL for SoC applications

IEEE Journal of Solid-State Circuits • 2004
View 2 Excerpts

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