A Hybrid Power Model for RTL Power Estimation

Abstract

We propose a hybrid power model for estimating the power dissipation of a design at the RT-level. This new model combines the advantages of both RT-level and gate-level approaches. We investigate the relationship between steadystate transition power and overall power dissipation. We observe that, statistically, two input sequences causing similar amount of steady-state transitions will exhibit similar overall power dissipation for an RTL module. Based on this observation, we propose a method to construct a hybrid power model for RTL modules. We further propose a hierarchical power estimation method for estimating the power dissipation of datapath consisting of RTL modules. Experimental results show that, for full-chip power estimation, the estimation time of the technique based on our power models is on average 275 times faster than directly running a commercial transistor-level power simulator, and the errors are less than 6% as compared to the transistor-level power simulation results.

DOI: 10.1109/ASPDAC.1998.669550

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@inproceedings{Jiang1998AHP, title={A Hybrid Power Model for RTL Power Estimation}, author={Yi-Min Jiang and Shi-Yu Huang and Kwang-Ting Cheng and Deborah C. Wang and ChingYen Ho}, booktitle={ASP-DAC}, year={1998} }