A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management

@article{Gmieux2018AHA,
  title={A Hybrid Architecture With Low Latency Interfaces Enabling Dynamic Cache Management},
  author={Michel G{\'e}mieux and Meng Li and Yvon Savaria and Jean-Pierre David and Guchuan Zhu},
  journal={IEEE Access},
  year={2018},
  volume={6},
  pages={62826-62839}
}
The main focus of the dominant technologies in the high performance computation (HPC) market, such as GPU and multicore systems, is put on processing power, while much less attention has been paid to communication delays inside hybrid architectures. To fill this gap, this paper presents an experimental study on Intel’s Broadwell Xeon multicore processor with integrated Arria 10 FPGA capabilities to characterize the communication delays between CPUs and the FPGA, using both the low latency cache… CONTINUE READING

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