A Highly-Stable Nanometer Memory for Low-Power Design

@article{Lin2008AHN,
  title={A Highly-Stable Nanometer Memory for Low-Power Design},
  author={Sheng Ta Lin and Yong-Bin Kim and Fabrizio Lombardi},
  journal={2008 IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems},
  year={2008},
  pages={17-20}
}
A nine transistor (9T) cell at a 32nm feature size in CMOS is proposed to accomplish improvements in stability as well as power dissipation compared with previous designs for low-power memory operation. Initially, this paper shows that the proposed 9T SRAM cell can be used for robust, high-density design. Then, an optimum sizing is found for this 9T cell by considering stability, energy consumption, and performance. A write bitline balancing scheme is proposed to further reduce the power… CONTINUE READING
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