A Highly Parallel FPGA Implementation of Sparse Neural Network Training

@article{Dey2018AHP,
  title={A Highly Parallel FPGA Implementation of Sparse Neural Network Training},
  author={Sourya Dey and Diandian Diana Chen and Zongyang Li and Souvik Kundu and Kuan-Wen Huang and Keith M. Chugg and Peter A. Beerel},
  journal={2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig)},
  year={2018},
  pages={1-4}
}
This paper describes the development of an FPGA implementation of a parallel and reconfigurable architecture for sparse neural networks, capable of on-chip training and inference. The network connectivity uses pre-determined, structured sparsity to significantly reduce complexity by lowering memory and computational requirements. The architecture uses a notion of edge-processing, leading to efficient pipelining and parallelization. Moreover, the device can be reconfigured to trade off resource… CONTINUE READING
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