A High Speed Cmos Incrementer/decrementer Circuit with Reduced Power Delay Product

Abstract

– A novel circuit topology for the CMOS based Incrementer/Decrementer circuit is presented in this paper. The design methodology is extensively based on Domino logic and it utilizes a simple two level look-ahead structure. The highly parallel, regular structure of the proposed 8-bit decision module (DM) macro cell makes this design, especially advantageous for constructing higher order versions, facilitating an easier layout and test mechanism. For a 32-bit Incrementer/Decrementer circuit, based upon the proposed design, the savings in power delay product (PDP) are of the order of 65 % and 38 %, with a significant reduction in the number of transistors, in comparison with the best decision module designs reported in [1] and [2], based on a similar MOSIS 0.6 μm CMOS technology. Key-Words: Decision Module (DM), Incrementer/Decrementer, Proposed Priority Resolver (PPR), High Speed (HS) High Speed Low Power (HSLP), Power Delay Product (PDP)

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Cite this paper

@inproceedings{Balasubramanian2005AHS, title={A High Speed Cmos Incrementer/decrementer Circuit with Reduced Power Delay Product}, author={Pranav Balasubramanian and Raghavan Chinnadurai}, year={2005} }