• Corpus ID: 18048553

A High-Speed 64-Bit Binary Comparator Anjuli ,

  title={A High-Speed 64-Bit Binary Comparator Anjuli ,},
  author={Satyajit Anand},
A high-speed 64-bit binary comparator is proposed in this brief. Comparison is most basic arithmetic operation that determines if one number is greater than, equal to, or less than the other number. Comparator is most fundamental component that performs comparison operation. This brief presents comparison of modified and existing 64-bit binary comparator designs concentrating on delay. Means some modifications are done in existing 64-bit binary comparator design to improve the speed of the… 



A new low-power high-speed single-clock-cycle binary comparator

This paper presents a new ultra-low power high-speed single-clock-cycle binary comparator. It is based on a novel parallel-prefix algorithm which drastically reduces the switching activity of the

Fast Low-Cost Implementation of Single-Clock-Cycle Binary Comparator

  • S. PerriP. Corsonello
  • Engineering, Computer Science
    IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2008
Comparison with the fastest comparator known in the literature demonstrates that, at a parity of technology used, the novel architecture is ~ 12% faster and requires ~ 69% less transistors.

A Low-Power High-Performance Single-Cycle Tree-Based 64-Bit Binary Comparator

A single-cycle 64-bit binary comparator utilizing a radix-2 tree structure is proposed in this brief, specifically designed for static logic to achieve both low-power and high-performance operation, particularly at low-input data activity environments.

High-performance single clock cycle CMOS comparator

A novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm, which results in significant improvement over the traditional design.

A mux-based High-Performance Single-Cycle CMOS Comparator

  • H. LamC. Tsui
  • Engineering
    IEEE Transactions on Circuits and Systems II: Express Briefs
  • 2007
A new architecture for high-fan-in CMOS comparator is proposed, based on a hierarchical two-stage comparator structure and a dynamic MUX is used instead of a comparator in the second stage of the structure to significantly improve the overall delay of the high- fan-in comparators.

High-performance and power-efficient CMOS comparators

Post-layout simulation results show that a 64-b comparator designed with the proposed techniques in a 3-V 0.6-/spl mu/m CMOS technology is 16% faster, 50% smaller, and 79% more power efficient as compared with the all-n-transistor comparator, which is the fastest among the conventional comparators.

Low-power logic styles: CMOS versus pass-transistor logic

This paper shows that complementary CMOS is the logic style of choice for the implementation of arbitrary combinational circuits if low voltage, low power, and small power-delay products are of concern.

Low-Power Digital VLSI Design: Circuits and Systems

This paper presents a methodology for designing low-Voltage Low-Power VLSI CMOS Circuit Design that addresses the challenge of integrating low-voltage components into a coherent system.

CMOS Digital Integrated Cir-cuits: Analysis and Design

Through rigorous analysis of CMOS circuits in this text, students will be able to learn the fundamentals ofCMOS VLSI design, which is the driving force behind the development of advanced computer hardware.

Digital Design " . (Pearson Education Asia

  • Digital Design " . (Pearson Education Asia
  • 2002