A High Performance Architecture for Implementation of 2-D Convolution with Quadrant Symmetric Kernels
@article{Zhang2008AHP, title={A High Performance Architecture for Implementation of 2-D Convolution with Quadrant Symmetric Kernels}, author={M. Zhang and H. Ngo and Adam R. Livingston and V. Asari}, journal={International Journal of Computers and Applications}, year={2008}, volume={30}, pages={298 - 308} }
Abstract The design of a high performance digital architecture for computing 2-D convolution, utilizing the quadrant symmetry of the kernels, is proposed in this paper. Pixels in the four quadrants of the kernel region, with respect to an image pixel, are considered simultaneously for computing the partial products of the convolution sum. A novel data handling strategy, to identify pixels to be fed to different processing elements, helps reduce the data storage requirements significantly in the… CONTINUE READING
Topics from this paper
4 Citations
Rapid prototyping of an automated video surveillance system: a hardware-software co-design approach
- Computer Science, Engineering
- Defense + Commercial Sensing
- 2011
- PDF
References
SHOWING 1-10 OF 24 REFERENCES
An efficient programmable 2-D convolver chip
- Computer Science
- ISCAS '98. Proceedings of the 1998 IEEE International Symposium on Circuits and Systems (Cat. No.98CH36187)
- 1998
- 13
Constant coefficient multiplication in FPGA structures
- Computer Science
- Proceedings of the 26th Euromicro Conference. EUROMICRO 2000. Informatics: Inventing the Future
- 2000
- 44
Reconfigurable pipelined 2-D convolvers for fast digital signal processing
- Computer Science
- IEEE Trans. Very Large Scale Integr. Syst.
- 1999
- 139
- PDF
Parallel 2-D Convolution on a Mesh Connected Array Processor
- Computer Science, Medicine
- IEEE Transactions on Pattern Analysis and Machine Intelligence
- 1987
- 78
An advanced programmable 2D-convolution chip for, real time image processing
- Computer Science
- 1991., IEEE International Sympoisum on Circuits and Systems
- 1991
- 14
Efficient design and implementation of image processing algorithms on reconfigurable hardware using Handel-C
- Computer Science
- 2003
- 5
A custom chip set for real-time image processing
- Computer Science
- ICASSP '86. IEEE International Conference on Acoustics, Speech, and Signal Processing
- 1986
- 22
Two-level pipelined systolic array for multidimensional convolution
- Computer Science
- Image Vis. Comput.
- 1983
- 39
- PDF
An improved search algorithm for the design of multiplierless FIR filters with powers-of-two coefficients
- Mathematics, Computer Science
- 1989
- 468