A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size

@inproceedings{Inoue2000AHO,
  title={A High-Performance/Low-Power On-Chip Memory-Path Architecture with Variable Cache-Line Size},
  author={Katsuya Inoue and Koji Kai and Kazuaki Murakami},
  year={2000}
}
SUMMARYThis paper proposes an on-chip memory-path architectureemploying the dynamically variable line-size (D-VLS) cache forhigh performance and low energy consumption. The D-VLScache exploits the high on-chip memory bandwidth attainableon merged DRAM/logic LSIs by replacing a whole large cacheline in one cycle. At the same time, it attempts to avoid frequentevictions by decreasing the cache-line size when programs havepoor spatial locality. Activating only on-chip DRAM subarrayscorresponding… CONTINUE READING

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