A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

@article{Madsen2015AH3,
  title={A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process},
  author={Kristian N. Madsen and Timothy D. Gathman and Saeid Daneshgar and Thomas C. Oh and James Chingwei Li and James F. Buckwalter},
  journal={IEEE Journal of Solid-State Circuits},
  year={2015},
  volume={50},
  pages={2692-2702}
}
A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- Ω interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of… CONTINUE READING

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