A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers

@inproceedings{Claver2006AHN,
  title={A Hardware NIC Scheduler to Guarantee QoS on High Performance Servers},
  author={Jos{\'e} M. Claver and Manel Canseco and P. Agust{\'i} and German Leon},
  booktitle={ISPA},
  year={2006}
}
In this paper we present the architecture and implementation of a hardware NIC scheduler to guarantee QoS on servers for high speed LAN/SAN. Our proposal employs a programmable logic device based on an FPGA in order to store and update connection states, and to decide what data stream is to be sent next. The network architecture is connection-oriented and reliable, based on credit flow control. The architecture scales from 4 to 32 streams using a Xilinx Virtex 2000E. It supports links with… CONTINUE READING