A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation

Abstract

We present an efficient optimization scheme for gate sizing in the presence of process variations. Our method is a worst case design scheme; however, it reduces the pessimism involved in traditional worst case methods by incorporating the effect of spatial correlations in the optimization procedure. The pessimism reduction is achieved by employing a bounded… (More)
DOI: 10.1109/TCAD.2007.913391

Topics

11 Figures and Tables

Cite this paper

@article{Singh2008AGP, title={A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation}, author={Jaskirat Singh and Zhi-Quan Luo and Sachin S. Sapatnekar}, journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, year={2008}, volume={27}, pages={295-308} }