A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes

@article{Lesaicherre1994AGD,
  title={A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes},
  author={P. Y. Lesaicherre and Shintaro Yamamichi and Hiromu Yamaguchi and K. Takemura and H. Watanabe and Ken Tokashiki and Keiji Satoh and T. Sakuma and M Yoshida and S. Ohnishi and K. Nakajima and Kentaro Shibahara and Yuto Miyasaka and Hirotaka Ono},
  journal={Proceedings of 1994 IEEE International Electron Devices Meeting},
  year={1994},
  pages={831-834}
}
A new stacked capacitor technology with high permittivity ECR MOCVD SrTiO/sub 3/ films on 1 Gbit compatible RuO/sub 2/TiN storage nodes was developed for Gigabit-scale DRAMs. A cell capacitance of 25 fF and leakage current density of 8/spl times/10/sup -7/ A/cm/sup 2/ can be achieved with this capacitor technology, using 0.5 /spl mu/m high stacked storage electrodes in a 0.125 /spl mu/m/sup 2/ capacitor area. Fine storage RuO/sub 2/TiN electrodes were patterned down to 0.2 /spl mu/m by electron… 

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