A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes

  title={A Gbit-scale DRAM stacked capacitor technology with ECR MOCVD SrTiO/sub 3/ and RIE patterned RuO/sub 2/TiN storage nodes},
  author={P. Y. Lesaicherre and Shintaro Yamamichi and Hiromu Yamaguchi and K. Takemura and H. Watanabe and Ken Tokashiki and Keiji Satoh and T. Sakuma and M Yoshida and S. Ohnishi and K. Nakajima and Kentaro Shibahara and Yuto Miyasaka and Hirotaka Ono},
  journal={Proceedings of 1994 IEEE International Electron Devices Meeting},
A new stacked capacitor technology with high permittivity ECR MOCVD SrTiO/sub 3/ films on 1 Gbit compatible RuO/sub 2/TiN storage nodes was developed for Gigabit-scale DRAMs. A cell capacitance of 25 fF and leakage current density of 8/spl times/10/sup -7/ A/cm/sup 2/ can be achieved with this capacitor technology, using 0.5 /spl mu/m high stacked storage electrodes in a 0.125 /spl mu/m/sup 2/ capacitor area. Fine storage RuO/sub 2/TiN electrodes were patterned down to 0.2 /spl mu/m by electron… 

Figures from this paper

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs
A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing
Giga-bit scale DRAM cell with new simple Ru/(Ba,Sr)TiO/sub 3//Ru stacked capacitors using X-ray lithography
We have fabricated experimental memory cell arrays with a unit cell size of 0.29 /spl mu/m/sup 2/ (0.38 /spl mu/m/spl times/0.76 /spl mu/m). The layout was designed for a half-pitch 8F/sup 2/ cell
Novel stacked capacitor technology for 1 Gbit DRAMs with CVD-(Ba,Sr)TiO/sub 3/ thin films on a thick storage node of Ru
Simple stacked cell capacitors for 1 Gbit DRAMs have been constructed with a thick storage node of ruthenium (Ru) and high dielectric constant CVD-(Ba,Sr)TiO/sub 3/ films of equivalent oxide
Ta/sub 2/O/sub 5/ capacitors' dielectric material for giga-bit DRAMs
We fabricated 256-Mbit DRAM cells using a 0.5 /spl mu/m high CROWN capacitor with crystallized Ta/sub 2/O/sub 5/ dielectric film. We confirmed that the crystallized Ta/sub 2/O/sub 5/ (3.3 nm of
Ferroelectric nonvolatile memory technology: applications and integration challenges
Summary form only given. We discuss different integration approaches, their challenges, and problems specific to the integration of ferroelectric materials into Si-CMOS. The focus is on our ongoing
Development of MIM/Ta2O5 capacitor process for 0.10-µm DRAM
As the fabrication dimension becomes smaller, it becomes increasingly difficult to ensure storage capacitance for DRAM. For this reason, a capacitor process using high-permittivity insulating films
High-Performance$hboxSrTiO_3$MIM Capacitors for Analog Applications
TaN/SrTiO<sub>3</sub>/TaN capacitors with a capacitance density of 28-35 fF/mum<sup>2</sup> have been developed by using a high-kappa (kappa=147-169) SrTiO<sub>3</sub> dielectric containing
Charge trapping and degradation in high-permittivity TiO2 dielectric films
Suitable replacement materials for ultrathin SiO/sub 2/ in deeply scaled MOSFETs such as lattice polarizable films, which have much higher permittivities than SiO/sub 2/, have bandgaps of only 3.0 to
Impact of time dependent dielectric breakdown and stress-induced leakage current on the reliability of high dielectric constant (Ba,Sr)TiO/sub 3/ thin-film capacitors for Gbit-scale DRAMs
Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO/sub 3/ (BST) thin films. Both time to breakdown (T/sub BD/)
Novel ferroelectric epitaxial (Ba,Sr)TiO/sub 3/ capacitor for deep sub-micron memory applications
A novel ferroelectric capacitor cell was developed using a (Ba,Sr)TiO/sub 3/ (BSTO)/SrRuO/sub 3/ (SRO) heteroepitaxial technique on Si and strontium titanate substrates. Distinct ferroelectricity


Structural and Electrical Characterization of SrTiO3 Thin Films Prepared by Metal Organic Chemical Vapor Deposition
SrTiO3 thin films were prepared on Si and Pt/TaOx/Si substrates by Sr(DPM)2/Ti(i-OC3H7)4/O2/Ar chemical vapor deposition (CVD), using a simple vaporizing-and-transport source delivery system. A
High dielectric constant (Ba,Sr)TiO3 thin films prepared on RuO2/sapphire
RuO2 thin films have been prepared onto sapphire by reactive sputtering with Ar+O2 plasma and their application as the bottom electrode in the high dielectric constant (Ba0.5Sr0.5)TiO3 (BST) thin
Preparation of SrTiO 3 Thin Films by Ecr and Thermal Mocvd
SrTiO 3 thin films were prepared by ECR and thermal MOCVD. In thermal-CVD mode, Sr content and Ti content were at a maximum at 0.56 Torr. Results showed that SrO deposition is a surface reaction