A GALS Infrastructure for a Massively Parallel Multiprocessor

  title={A GALS Infrastructure for a Massively Parallel Multiprocessor},
  author={Luis A. Plana and Stephen B. Furber and Steve Temple and Muhammad Mukaram Khan and Yebin Shi and Jian Wu and Shufan Yang},
  journal={IEEE Design & Test of Computers},
This case study focuses on a massively parallel multiprocessor for real-time simulation of billions of neurons. Every node of the design comprises 20 ARM9 cores, a memory interface, a multicast router, and two NoC structures for communicating between internal cores and the environment. The NoCs are asynchronous; the cores and RAM interfaces are synchronous. This GALS approach decouples clocking concerns for different parts of the die, leading to greater power efficiency. 
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