A Fully Integrated 4 $\times$ 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 $\mu{\hbox {m}}$ CMOS SOI Technology

@article{Narasimha2007AFI,
  title={A Fully Integrated 4 \$\times\$ 10-Gb/s DWDM Optoelectronic Transceiver Implemented in a Standard 0.13 \$\mu\{\hbox \{m\}\}\$  CMOS SOI Technology},
  author={Adithyaram Narasimha and Behnam Analui and Yu-An Liang and T. J. Sleboda and Sherif Abdalla and Erwin Balmater and Steffen Gloeckner and Drew Guckenberger and Mark S. Harrison and R. K. J. Koumans and Daniel Kucharski and Attila Mekis and Sina Mirsaidi and Dan Song and Thierry Pinguet},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={2736-2744}
}
Optical and electronic building blocks required for DWDM transceivers have been integrated in a 0.13 mum CMOS SOI technology. Using these building blocks, a 4 x 10-Gb/s single-chip DWDM optoelectronic transceiver with 200 GHz channel spacing has been demonstrated. The DWDM transceiver demonstrates an unprecedented level of optoelectronic system integration, bringing all required optical and electronic transceiver functions together on a single SOI substrate. An aggregate data rate of 40 Gb/s… CONTINUE READING
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