Traffic congestion is a severe problem in this new era of growing vehicle population in all the developing countries. This is a bold signal to the modern age technology for a major improvement and innovation in the existing traffic control system. The most widely used traffic control system uses a simple time-based system and it works on a time interval basis. It is an automatic system but for modern age random and non-uniform traffic, it is inefficient. The advance automatic systems use the image processing technology or advance communication system to communicate and route. It might be used in the developing countries but it is very much complex and expensive too. The practical implementation of this advance traffic control system is also arduous in countries like India. In this paper, a low cost, real-time, system-on-chip (SoC), application specific automatic traffic control system has been proposed and implemented for four way traffic and the delay between two states can be changed manually, depending upon the density of the traffic. It is being implemented using Hardware Description Language (HDL) on a Field Programmable Gate Array (FPGA) chip without using any other hardware resources or high level languages. The physical attribute of an FPGA chip, being compact in size and low in power consumption, makes it an ideal platform for the implementation. The complete architecture of the proposed traffic control system has been designed using Finite State Machine (FSM) based approach and it contains three different modules. The modules are System Initialization Module (SIM), Signal Generation Module (SGM) and Delay Control Module (DCM). The architecture is completely synthesized for Spartan 3E xc3s500e-4-fg320 FPGA with only 1% of the total logic utilization. Result obtains from a practical set-up of a four-way traffic system, where the signals are controlled by the proposed controller and the toy cars and the density of the traffic has been controlled manually.