Corpus ID: 14802958

A Floating Point Multiplier based FPGA Synthesis for Neural Networks Enhancement

@inproceedings{Benrekia2010AFP,
  title={A Floating Point Multiplier based FPGA Synthesis for Neural Networks Enhancement},
  author={F. Benrekia and M. Attari},
  year={2010}
}
FPGA (Field Programmable Gate Array) implementation of Artificial Neural Networks (ANNs) calls for multipliers of various word lengths. In this paper, a new approach for designing a FloatingPoint Multiplier (FPM) is developed and tested using VHDL. With VHDL (Very High Description Language) analyzer and logic synthesis software, hardware prototypes could be implemented in FPGA. I. Introduction Recently, several applications have been implemented with FPGA using ANNs architecture [1],[2]. These… Expand
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