A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family

@article{Bucci2012AFF,
  title={A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family},
  author={Marco Bucci and Luca Giancane and Raimondo Luzzi and Alessandro Trifiletti},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2012},
  volume={20},
  pages={2128-2132}
}
This paper investigates the design of a data flip-flop compatible with the three-phase dual-rail pre-charge logic (TDPL) family. TDPL is a differential power analysis (DPA) resistant dual-rail logic style whose power consumption is insensitive to unbalanced load conditions, based on a three phase operation where, in order to obtain a constant energy consumption, an additional discharge phase is performed after pre-charge and evaluation. In this work, the TDPL basic gates operation is shortly… CONTINUE READING
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