A Fault Tolerant Hierarchical Network on Chip Router Architecture

Abstract

Continuing advances in the processing technology, along with the significant decreases in the feature size of integrated circuits lead to increases in susceptibility to transient errors and permanent faults. Network on Chips (NoCs) have come to address the demands for high bandwidth communication among processing elements. The structural redundancy… (More)
DOI: 10.1109/DFT.2011.12

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