A Fast Locking Phase-Locked Loop with Low Reference Spur

  title={A Fast Locking Phase-Locked Loop with Low Reference Spur},
  author={M. Abedi and J. Y. Hasani},
  journal={Electrical Engineering (ICEE), Iranian Conference on},
  • M. Abedi, J. Y. Hasani
  • Published 2018
  • Computer Science
  • Electrical Engineering (ICEE), Iranian Conference on
This paper presents a 3.2GHz dual loop PLL suitable for WiMAX applications which offers high speed locking, low reference spur, and low power consumption. We utilized Aperture Phase Detection (APD) mechanism in order to be able to turn off the blocks associated with frequency locked loop (FLL) in locked state, thereby reducing the overall power consumption. In the proposed dual-loop PLL, we adopted a new technique to decrease the dead zone (DZ) in DZ-creator circuit and speed up the frequency… Expand
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