A FPGA-based low-cost real-time wavelet packet denoising system

Abstract

Most existing wavelets are irrational, which are inefficient in hardware implementation and have expensive cost of resources. Based on rational wavelets, we establish a real-time wavelet packet denoising system, which greatly improves the implementation efficiency on FPGA chips. The experimental results reveal that rational 9–7 wavelet decomposition… (More)

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