Corpus ID: 10701072

A FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP FOR DC MOTOR CONTROL

@inproceedings{Onea2009AFI,
  title={A FPGA IMPLEMENTATION OF A PHASE LOCKED LOOP FOR DC MOTOR CONTROL},
  author={A. Onea},
  year={2009}
}
The paper proposes a way of implementing a phase locked loop (PLL) motor speed controller. The main emphasis is on the FPGA implementation of the digital PLL. The closed loop sensing element is an optical tachometer, which outputs an impulse train with a frequency proportional to the motor rotational speed. This impulse train will be synchronized by the PLL to a reference impulse train of a given precise frequency, generated inside the FPGA from a quartz crystal oscillator. The phase difference… Expand
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Resursele folosite din dispozitivul FPGA sunt sub 10% din disponibil
  • Resursele folosite din dispozitivul FPGA sunt sub 10% din disponibil
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