A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT

  title={A FPGA-Based Dual-Pixel Processing Pipelined Hardware Accelerator for Feature Point Detection Part in SIFT},
  author={Jingbang Qiu and Tianci Huang and Takeshi Ikenaga},
  journal={2009 Fifth International Joint Conference on INC, IMS and IDC},
SIFT is regarded as one of the most robust feature point detection algorithms in CV field. [...] Key Result Our proposal is suitable as a real-time SIFT system structure.Expand
High-Performance SIFT Hardware Accelerator for Real-Time Image Feature Extraction
A segment buffer scheme is successfully developed that could not only feed data to the computing modules in a data-streaming manner, but also reduce about 50% memory requirement than a previous work. Expand
Embedded hardware architectures for scale and rotation invariant feature detection
Three novel, efficient, scalable architectures for the keypoint detection step are presented, based on parallelizable and pipelined computational flow, which reduce the time taken for key point detection by more than 54%, 91% and 88% respectively as compared to existing designs. Expand
Real-time implementation of SIFT feature extraction algorithms in FPGA
Experimental results indicate that the improved SIFT algorithm on FPGA hardware platform has high stability, low algorithm complexity and high accuracy, meanwhile, shows up good real-time capability. Expand
An optimized FPGA implementation based on scale invariant feature transform feature points detection
An optimized FPGA implementation of SIFT (Scale Invariant Feature Transform) algorithm which has large amount of calculation and can be highly paralleled so that it can be accelerated on hardware is proposed. Expand
ASP-SIFT: Using Analog Signal Processing Architecture to Accelerate Keypoint Detection of SIFT Algorithm
An analog signal processing architecture, analog signalprocessing (ASP)-SIFT, is proposed in this article, which aims to reduce processing time and energy cost while executing SIFT. Expand
Multicore Computing for SIFT Algorithm in MATLAB® Parallel Environment
  • Hua Cao, Jiazhong Chen
  • Computer Science
  • 2012 IEEE 18th International Conference on Parallel and Distributed Systems
  • 2012
This paper tries to have a view for using the Matlab parallel toolbox to accelerate the SIFT algorithm by two schemes of task-par parallelism and data-parallelism modal, and shows that the parallel versions of former sequential algorithm with simple modifications achieve the speedup up to 6.6 times. Expand
SIFT-based low complexity keypoint extraction and its real-time hardware implementation for full-HD video
  • T. Suzuki, T. Ikenaga
  • Computer Science
  • Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference
  • 2012
This paper proposes a low complexity keypoint extraction algorithm based on SIFT descriptor and utilization of the database, and its real-time hardware implementation for Full-HD resolution video. Expand
Overview of approaches for accelerating scale invariant feature detection algorithm
This paper divides the researches into three different categories, that is, optimizing parallel algorithms based on general purpose multi- core processors, designing customized multi-core processor dedicated for SIFT and implementing SIFT based FPGA (Field Programmable Gate Arrays). Expand
Efficient VLSI design for SIFT feature description
This work first investigates the performance analysis for SIFT and then employs the proper hardware circuit to implement the feature description process, and adopts the pipelining technique to increase the speed of the design. Expand
A real-time embedded architecture for SIFT
This paper presents a low-cost embedded system based on a new architecture that successfully integrates FPGA and DSP that can detect SIFT feature and extract SIFT descriptor for detected features in real-time. Expand


A Hardware Accelerator with Variable Pixel Representation & Skip Mode Prediction for Feature Point Detection Part of SIFT Algorithm
This paper proposes a hardware accelerator structure of the Feature Point Detection part in SIFT which is possible to implement on FPGA and applies integer-based Variable Pixel Representation which helps to reach real-time processing. Expand
SIFT Implementation and Optimization for General-Purpose GPU
Methods and techniques that take advantage of modern graphics hardware for real-time tracking and recognition of feature-points and the generation of feature vectors from input images in the various stages are presented. Expand
A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection
The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several hardware-orientated optimizations on performance, area and accuracy. Expand
GPU-based Video Feature Tracking And Matching
Novel implementations of the KLT feature track- ing and SIFT feature extraction algorithms that run on the graphics processing unit (GPU) and is suitable for video analysis in real-time vision systems. Expand
Object recognition from local scale-invariant features
  • D. Lowe
  • Mathematics, Computer Science
  • Proceedings of the Seventh IEEE International Conference on Computer Vision
  • 1999
Experimental results show that robust object recognition can be achieved in cluttered partially occluded images with a computation time of under 2 seconds. Expand
Distinctive Image Features from Scale-Invariant Keypoints
The Scale-Invariant Feature Transform (or SIFT) algorithm is a highly robust method to extract and consequently match distinctive invariant features from images. These features can then be used toExpand
Exploration of large unknown planetary environments will rely on rovers that can autonomously cover distances of kilometres and maintain precise information about their location with respect to localExpand
A GPU implementation of the SIFT algorithm: An MSc Project Proposal
  • 2007
Eric McKenzie , " A GPU implementation of the SIFT algorithm : An MSc Project Proposal "
  • " A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection " IEEE Transaction on Circuits and Systems for Video Technology